The gate terminal - Polysilicon or Metal?

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The earliest technologies of the MOSFET used a metal for the gate (not self-aligned) terminal. The threshold voltage (and consequently the drain to source on-current) is determined by the work function difference between the gate material and channel material (essentially the substrate material). When metal was used as gate material, the large transistor sizes led to large gate voltages (3V to 5V), the threshold voltage (resulting from the work function difference between a metal gate and silicon channel) could still be overcome by the applied gate voltage (|VG - VTH| > 0). As transistor sizes were scaled down, the applied signal voltages were lowered to avoid gate oxide breakdown, hot-electron reduction, power consumption reduction etc. A transistor with a high threshold voltage would become non-operational under these new conditions. Thus, poly-crystalline silicon (polysilicon) became the modern gate material because it is the same chemical composition as the silicon channel beneath the gate oxide. In inversion, the work-function difference is close to zero, making the threshold voltage lower and ensuring the transistor can be turned on.

Another advantage of using polysilicon was the complexity involved in fabrication processes. The gate material was deposited prior to certain high-temperature processes in order to make better performing transistors. At these high temperatures, the metal gates would melt, thus necessitating a high melting point material such as polysilicon (poly-crystalline silicon). Theses dis-advantages could be negated using a metal alloy instead of a single metal. Such alloys, at high temperatures cause a short circuit between the diffused source & drain and across the junction. These shorts caused irreparable circuit discrepancies.

Using self-aligned gates also ensured diffusion of source & drain with a gate in place, which leads to a perfectly aligned channel, thus reducing the steps involved in lithography. This method also diminished the probability of non-aligned layers. Polysilicon was seen as more advantageous in this regard, as it was easy.

However, when the transistors are extremely scaled down (in orders of nm), it is necessary to make the gate dielectric layer very thin, around 1 nm in the most recent technologies. A phenomenon called the poly depletion is observed at these sizes, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion region. To negate this phenomenon, a metal gate is being preferred again. Metals such as tantalum, tungsten, tantalum nitride, and titanium nitride, usually in conjunction with high-k dielectrics.

Metals do not require doping since they have excess electrons owing to their metallic nature. Metals also offer lower resistance at practical doping concentrations. The strain capacity on the channel can be improved by the metal gate. Moreover, this enables less current perturbations (vibrations) in the gate.

The primary requirement for a prospective metal gate technology is attaining correct work functions for setting symmetrical threshold voltages for NMOS and PMOS. A key requirement (for a gate-first process) is also the ability to withstand source/drain dopant activation anneals, which is usually done at 1000°C for 5 seconds. This means that the metal must be chemically stable with the chosen dielectric.

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