The CMOS Transistor

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Introduction

CMOS stands for ‘Complementary Metal Oxide Semiconductor’. It is called Complementary as it contains two different types of semiconductor in the transistor – n-type & p-type. In an n-type, concentration of electrons is higher than that of holes (a place where an electron can exist, but is not). A p-type is chemically opposite to an n-type – hole concentration is higher than of electrons.

CMOS is a voltage controlled device and has varied applications: sensors, integrated circuits, converters, micro-processors, micro-controllers, memory modules.

A CMOS primarily has 3 body parts:

  1. Source
  2. Gate
  3. Drain
In practicality, a CMOS also has a fourth terminal known as ‘Bulk Terminal’. It is generally assumed that this terminal is connected to the source. It has no impact on working of the transistor, it also does not affect the properties of the transistor
.
CMOS transistors are very efficient for their use of power. An added advantage is that the complementary semiconductors work together to obtain a controlled output.

Layout of a CMOS

Image result for structure of a cmos and nmos
The basic structure of an NMOS has two heavily doped N-wells on a P type substrate. These N-wells act as a source (S) and drain (D). On top of the N-well structure is a thin layer of Silicon Oxide which is present as an insulator. The device also has a layer of either metal or polycrystalline silicone (polysilicon) above the thin insulating layer. The older devices used metal, hence the name Metal Oxide Semiconductor. However, the modern devices use polysilicon as the Gate (G). The source and drain are also attached with metal contacts to input and output the voltages. When the transistor is in ON state, an electric field is also present between the source and drain.

In case of an NMOS, the N-type diffusion regions are divided by the poly-silicon gate region and are symmetric. In PMOS, it is vice versa. The divided N-type diffusion regions are fixed with contacts and metal structures to facilitate voltages.

Operation of an NMOS transistor

The device conductivity depends on the voltage applied to the terminals. The amount of charge carriers is controlled by varying the width of the channel. The charge carriers enter via the source and exit via the drain. An initial positive voltage is applied at the gate and source (VGS). This causes the holes under the insulating layer to repel away further down the substrate. This causes a depletion region to be formed between the source and drain. This positive voltage also attracts electrons from the N+ drain and source. At this stage, the area between resembles an N-type silicon and the transistor is still in OFF state.

The voltage at the gate and source is increased, at a critical voltage point, the area is almost devoid of holes and resembles a strongly N- doped region. The transistor is in ON. A conducting channel is formed. This facilitates passage of electric current. Hence it is also called as inversion layer – the area which was initially P – type (as part of the substrate) has been ‘inversed’ to an N type by applying a voltage. This voltage point is called as the threshold voltage (VTH).

At this stage that the voltage at the drain and source (VDS) is non-existent (0V). The current increases exponentially with voltage at this stage. Further increasing the voltage increases the number of electrons attracted to the inversion layer. But at this point, only a finite charge is available as there is no conducting material. The only conductance available is that from the doped region. Therefore, the current saturates after the voltage increases beyond the threshold voltage.

The above operation can simply be put as –

  • VGS < VTH – Depletion
  • VGS = VTH – Inversion
  • VGS > VTH – Saturation
With VGS > VTH, an increasing voltage at the drain and source (VDS) is applied. The drain is now positive compared to the source. Hence a horizontal electric field is applied to the current channel. This channel charge (QCH) causes an average electron drift velocity from source to drain. If td is the drift time required to cross the channel by an electron, the current ID can be derived as –

๐ผ๐ท=๐‘„๐ถ๐ป/๐‘ก๐‘‘ Amperes

The channel charge QCH is modulated by the VGS voltage that exceeds the threshold voltage VTH, i.e. VGS ‐ VTH. The channel voltage (VCH) is calculated using –

VCH = (๐‘‰๐บ๐‘†−๐‘‰๐‘‡๐ป)−๐‘‰๐ท๐‘† Volts

When current ID flows, the potential along the channel changes. At the source, it is 0V, and at the drain it is equal to voltage applied. The effective voltage is smallest at the source and largest at the drain. The effect of changing this voltage can be viewed as changing the channel resistance. It is also important to note that as VDS increases, the electric field on the current channel also increases.

Trans-conductance in a MOSFET

Trans-conductance is the property of certain electronic components or devices. Trans-conductance is the ratio of the current change at the output terminal to the voltage change at the input terminal. It is often represented by gm. It is represented by the unit ‘siemen (S)’, where 1 siemen is the equivalent of 1 ampere per volt. Trans-conductance may also be referred to as ‘transfer admittance’.
For a MOSFET, gm may be defined as the ratio of change in drain current to the change in gate-to-source voltage. It is assumed that the drain-to-source voltage is constant.


The trans-conductance is calculated by calculating the slope of the curve in the I-V characteristics of the MOS device (ID vs VGS). The figure below shows the graph of ID vs VGS of a MOS device along with calculation of trans-conductance.


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